1. Field of the Invention
This invention relates to a non-volatile memory device, and more particularly, it relates to a technology useful for a memory device which utilizes the Magneto Resistive (MR) effect enabled by the tunneling effect.
2. Background of the Invention
In recent years, attention has been given to a Random Access Memory (RAM) using the Magneto Resistive Effect, wherein the resistance value of a magnetic substance varies depending on the magnetization direction of the substance by virtue of Magneto Resistive Effect. RAM using the Magnetic Resistive Effect is referred to as MRAM (Magneto-resistive RAM). For the Magneto Resistive Effect, the anisotropic Magneto Resistive Effect (AMR) and giant Magneto Resistive Effect (GMR) are known. It has also been known that higher field sensitivity can be realized through the use of tunnel Magneto Resistive Effect (TMR), in which a tunnel current is used to achieve the Magneto Resistive Effect is also known.
A spin valve element using TMR, also referred to as a Magnetic Tunnel Junction (MTJ) element, has a laminated layer structure comprising an antiferromagnetic layer, ferromagnetic layer (pin layer), insulating layer (tunnel layer), and ferromagnetic layer (free layer). The antiferromagnetic layer functions to fix the magnetization direction of the ferromagnetic layer (pin layer) adjacent thereto, and the coincidence of the magnetization direction of the free layer and that of the pin layer causes a tunnel current flowing through the insulating layer. When the magnetization direction of the free layer is opposite to that of the pin layer, the current flowing through the insulating layer is smaller than when they coincide. That is, depending on the magnetization direction (the direction of electron spin) of the free layer, the resistance value of TMR elements in the direction of the lamination changes. Therefore, it is possible to construct a memory device in which the information of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is recorded into TMR elements with the magnetization direction of such free layers and then read out with a change in the resistance value of the TMR elements.
As will be apprecitiated by those skilled in the art, such a memory element MRAM using the TMR effect is of the non-volatile type and is also a static element, in which recorded contents are not destroyed by reading them. Further, the reading of information is only based on detecting a change in the resistance of TMR elements. Therefore, a basic cell for recording one bit requires only one selection transistor. From this fact, MRAM is capable of providing a packing density (i.e. low cost) as high as DRAM (Dynamic Random Access Memory) and implementing non-volatile memory devices such as EEPROM (electrical erasable Read Only Memory). In addition, it is possible for MRAM to implement a solid state memory element not requiring refresh operation same as SRAM (Static Random Access Memory). Further, MRAM has no limitation on the number of times that data can be re-written, as EEPROM has, and also have a higher rewrite speed as compared to EEPROM. Also, MRAM has a read speed and write speed as fast as DRAM. MRAM has many remarkable advantages as described above, it is expected that MRAM is a promising memory device replacing existing all solid state memory devices.
An access method for reading and writing from and to MRAM is dependent on the configuration of the memory cells and the placement of the bit lines and word lines. Hereinafter, for the cell configuration in which one memory cell is composed of one TMR element and one selection transistor, a reading and writing method will be described.
First, a typical structure of MRAM will be described. One end of a TMR element making up a memory cell is connected to the drain of a selection transistor, and the other end of the TMR element is connected to a bit line. The bit line is disposed above the TMR element in the cross-sectional view of the memory cell. The direction of extension of the bit line is referred to as a first direction. Since the memory cells are arranged in two dimensions with a matrix-like configuration in a memory array area, a plurality of memory cells (TMR elements) are connected to one bit line. This is similar to a typical DRAM. The drain of the selection transistor is usually connected to the TMR element through conductive plugs within a plurality of via holes or through holes and interconnect lines.
The source of the selection transistor is maintained at the ground potential, and the gate electrode of the selection transistor is formed as a portion of a word line extending in the second direction orthogonal to the first direction. The word line is made of a low resistive semiconductor material, such as doped polycrystalline silicon. Thus, the gate electrodes of the selection transistors arranged in the second direction forms a common word line. This is similar to DRAM.
Further, in the cross-sectional view of the TMR element, the word line is disposed extending in the second direction in a region below the TMR element.
The method for writing and reading will be described with respect to the memory cell having a structure as described above. First, the writing of information into the memory cell utilizes the bit line and word line. As described above, the bit lines and the write word lines are extending in different directions, and are disposed in a lattice-like arrangement with an orthogonal relationship. By selecting one bit line and one write word line a corresponding memory cell situated at the intersection of the two lines can be selected.
Currents in the predetermined directions are fed through the bit and write word lines selected. This makes the resultant of a magnetic field created by a current flowing through the bit line and a magnetic field created by a current flowing through the write word line. This composite magnetic field determines the magnetization direction of the free layer above-described. For example, the information corresponding to xe2x80x9c1xe2x80x9d makes the magnetization direction of the free layer opposite to that of the pin layer, thereby increasing the resistance value of the TMR element. On the other hand, the information corresponding to xe2x80x9c0xe2x80x9d makes the magnetization direction of the free layer coincident with that of the pin layer, thus decreasing the resistance value of the TMR element. Therein, the pin layer has been magnetized in a predetermined orientation, in advance.
In this way, in order to read information from the memory cells in which the information has been written, the bit lines and read word lines are used. In the same manner as described above, by selecting one bit line and one read word line, a memory cell situated at the intersection of the two lines is selected. By activating the gate electrode (read word line) of the selection transistor of the memory cell selected, the selection transistor is brought to the ON state, and thus a resistance value between the bit line and the ground is measured to detect the information (whether high resistance or low resistance). Thus, the information is read out.
As described above, an MRAM device has noticeable advantages over other memory devices, but also it has various problems in achieving high reliability and high integration into comercial application. For example, the problems include the reduction of variations in write magnetization and the stabilization of the pin layer. In particular, because such an MRAM device uses tunnel current, the insulating layers need to be made extremely thin, and as such improving the stability and uniformity of the insulating layers are significant challenges.
For example, as MRAM cell size is reduced, the flow of current per unit area of the TMR cells becomes larger, resulting in a deterioration of the reliability. There is a minimum current capacity required to detect a change in the resistance of a TMR element, independently of the degree of reduced size of the cells. Therefore, as TMR cells become smaller, the density of current flowing through the cells becomes higher. This is one of factors for low reliability of the insulating layer in an extremely thin film.
There is another problem that the element resistances varies due to the manufacturing process variations in the insulating layers, pin layers, and free layers. Such variations in the element resistance due to the manufacturing processes cause variations in changed portions of resistance of the free layers dependent on the magnetization direction. This may prevent appropriate reading of information. That is, when variations in changed portions of the resistance values are large, it is difficult to detect a change in the resistance value dependent on the magnetization direction. Further, when memory cells become smaller, the change in the resistance values also becomes smaller, and thus the effect of the variations in the resistance values becomes larger. When a change in the resistance is small, the influence of the variations can not be neglected. In addition, for a characteristic of magneto resistive elements, a problem has been pointed out that a change in the resistance value dependent on the magnetization direction (MR ratio) is reduced when a high bias voltage is applied to the magneto resistive elements.
It is an object of the invention to improve the reliability of MRAM recording. It is also another object of the invention to allow highly reliable reading of information, provided that a certain degree of variations in resistance values exists. It is a further object of the invention to lower the bias-voltage dependence of MR ratio of magneto resistive elements.
A brief summary of the present invention is given as follows. According to the invention, recording one bit of information in a memory cell includes a plurality of sub-cells each having magneto resistive elements connected in series or in parallel, and the memory cell is constructed such that a plurality of the magneto resistive elements are connected in series and in parallel in the whole memory cell by connecting the sub-cells in parallel or in series. This structure of the memory cell can reduce a current flowing through one magneto resistive element and thus suppress the deterioration in the reliability of the memory cell, caused by making the cell smaller. Because a plurality of the magneto resistive elements together record one bit of information, even if one of the magneto resistive elements have a smaller change in the resistance value, the reduced change in the resistance value of the whole memory cell can be made smaller. Further, when the magneto resistive elements are connected in series, the voltage applied to one element becomes small. Thereby, the bias-voltage dependence of the magneto resistive element becomes small, because, in the bias-voltage dependence of the magneto resistive element, the larger the voltage across one magneto resistive element is, the smaller the change in the resistance value (MR ratio) is.
Further, according to an aspect of the invention, a plurality of the memory cells connected in series or in parallel together may record one bit of information. The serial or parallel connection is made in a peripheral circuit of the memory cell. Thereby, in addition to the improvement of the reliability of recording information, the number of the memory cells used for recording one bit can be modified by changing the connections of interconnect lines in the peripheral circuit without changing the device design within the memory cell. For example, when the reliability of the magneto resistive elements is relatively low, the number of the memory cells used for recording one bit will be increased (that is, more memory cells are connected in series and in parallel), and when the reliability has been improved, one memory cell is used to record one bit.
The memory device according to the invention is a non-volatile memory device having a memory cell which includes a magneto resistive element having a resistance value that varies depending on the magnetization direction thereof and records one bit of information. The memory cell has plural sub-cells each including at least one of the magneto resistive element, and the sub-cells are connected in series or in parallel.
For example, the sub-cell may be composed of one parallel sub-cell having n1 magneto resistive elements connected in parallel and one selection transistor, and the memory cell may comprise n2 sub-cells connected in series. Wherein, n1 and n2 are respectively an integer greater than or equal to 2. Or, the sub-cell may be composed of one series sub-cell having n2 magneto resistive elements connected in series and one selection transistor, and the memory cell may comprise n1 sub-cells connected in parallel. Alternatively, the sub-cell is composed of one magneto resistive element and one selection transistor, and the memory cell comprises n2 parallel sub-cells connected in series, the parallel sub-cell comprising n1 sub-cells connected in parallel.
Further, the memory device according to an aspect of the invention may be a non-volatile memory device having a memory cell which includes a magneto resistive element having a resistance value that is variable depending on the magnetization direction thereof and records one bit of information. The memory cell may be composed of n2 parallel sub-cells connected in series and one selection transistor, wherein the parallel sub-cell is composed of n1 magneto resistive elements connected in parallel.
In an aspect of the invention, n1 and n2 can be assumed to be the same number. Further, in the above-described memory device, the writing of information into the memory cell can be performed by magnetizing into the same direction the free layers for all the magneto resistive elements included in the memory cell, and the reading of the information recorded in the memory cell can be performed by detecting the resistance value of the whole memory cell.
Further, the memory device according to an aspect of the invention can include a memory cell composed of one magneto resistive element and one selection transistor, a memory array having the memory cells arranged in two dimensions, a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in the memory cell, a second interconnect line extending in a second direction of the memory array and connected to one end of the memory cell, a third interconnect line extending in the second direction and connected to the other end of the memory cell. Wherein, a circuit for a memory cell having the ends of the second and third interconnect lines as its terminals is connected in series with a circuit for another memory cell adjacent thereto in the first direction, in a circuit area in the periphery of the memory array.
In this case, the writing of one bit of information into the non-volatile memory device can be performed by magnetizing into the same direction the free layers of the magneto resistive elements of a plurality of the memory cells which are disposed at the intersections of a plurality of the first interconnect lines and a plurality of the second interconnect lines. Further, the reading of one bit of information from the non-volatile memory device may be performed by inputting the same read control signal to the plurality of the first interconnect lines and detecting the resistance value between the second interconnection line and the third interconnection line of the circuits connected in series. The number of the plurality of the first interconnect lines may be the same with the number of the circuits connected in series.